The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
May. 29, 2008
Eric C. T. Harley, LaGrangeville, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Dominic J. Schepis, Wappingers Falls, NY (US);
Michael D. Steigerwalt, Newburgh, NY (US);
Linda Black, Fishkill, NY (US);
Rick Carter, Hopewell Junction, NY (US);
Eric C. T. Harley, LaGrangeville, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Dominic J. Schepis, Wappingers Falls, NY (US);
Michael D. Steigerwalt, Newburgh, NY (US);
Linda Black, Fishkill, NY (US);
Rick Carter, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries, Grand Cayman, KY;
Abstract
Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.