EPO Patents = 3 (Patent Applications = 1)

Average Co-Inventor Count = 2.4

ph-index = 7

Forward Citations = 260(Granted Patents)

Location History:

Nishishirakawa, JP (1999)
Fukushima-ken, JP (1999 - 2001)
Ome, JP (2004 - 2006)
Fukushima, JP (2005 - 2008)
Nishishirakawa-gun, JP (1997 - 2009)
Annaka, JP (2022)
Kashiwazaki, JP (2024)

Company Filing History:

11 out of 1,099

Shin-etsu Handotai Co., Ltd.

patents

6 out of 52,711

Kabushiki Kaisha Toshiba

4. 1 out of 832,680

Other

patents

where one patent can have more than one assignee

Years Active: 1997-2024

where 'Filed Patents' based on already Granted Patents

15 patents (USPTO):Sort by Forward Citations

Abstract keywords

1. 12027672 - Battery and battery pack (2024-07-02),

2. 11486833 - Method for evaluating edge shape of silicon wafer, apparatus for evaluating thereof, silicon wafer, method for selecting and method for manufacturing thereof (2022-11-01),

3. 7474386 - Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method (2009-01-06),

4. 7435662 - Method for manufacturing SOI wafer (2008-10-14),

5. 7365830 - Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method (2008-04-29),

6. 7230680 - Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method (2007-06-12),

7. 7149408 - Method and apparatus for editing video data (2006-12-12),

8. 6975960 - Method for evaluating wafer configuration, wafer, and wafer sorting method (2005-12-13),

9. 6828163 - Wafer shape evaluating method and device producing method, wafer and wafer selecting method (2004-12-07),

10. 6782241 - Radio device control terminal apparatus, radio system and multimedia system constitution method (2004-08-24),

11. 6306021 - Polishing pad, polishing method, and polishing machine for mirror-polishing semiconductor wafers (2001-10-23),

12. 5913719 - Workpiece holding mechanism (1999-06-22),

13. 5879220 - Apparatus for mirror-polishing thin plate (1999-03-09),

14. 5860853 - Apparatus for polishing wafers (1999-01-19),

15. 5700179 - Method of manufacturing semiconductor wafers and process of and (1997-12-23),

Title: The Innovative Contributions of Makoto Kobayashi

Introduction

Makoto Kobayashi is a prominent inventor based in Nishishirakawa-gun, Japan. He has made significant contributions to the field of technology, particularly in battery design and silicon wafer evaluation. With a total of 15 patents to his name, Kobayashi's work has had a lasting impact on various industries.

Latest Patents

Kobayashi's latest patents include advancements in battery and battery pack technology. One embodiment describes a battery that consists of an external container, an electrode group, and a sealing plate. The electrode group features a positive and negative electrode wound in a flat shape, with an insulating layer in between. The thicknesses of the positive and negative electrodes range from 0.03 mm to 0.08 mm. The design ensures that the thicknesses and dimensions meet specific criteria for optimal performance.

Another notable patent involves a method for evaluating the edge shape of silicon wafers. This method defines various shape parameters in a wafer cross-section and measures the edge shape to prevent potential issues during manufacturing. The calculated parameters allow for a precise evaluation of the silicon wafer's edge shape, enhancing the quality of the final product.

Career Highlights

Throughout his career, Kobayashi has worked with esteemed companies such as Shin-Etsu Handotai Co., Ltd. and Toshiba Corporation. His experience in these organizations has contributed to his expertise in developing innovative technologies.

Collaborations

Kobayashi has collaborated with notable colleagues, including Fumihiko Hasegawa and Tadahito Fujisawa. These partnerships have fostered a creative environment that has led to groundbreaking advancements in their respective fields.

Conclusion

Makoto Kobayashi's contributions to technology, particularly in battery design and silicon wafer evaluation, showcase his innovative spirit and dedication to advancing the industry. His numerous patents reflect his commitment to excellence and his impact on future technological developments.

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3 patents (EPO):

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1 patent pending (EPO):

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