The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2008

Filed:

Nov. 13, 2003
Applicant:

Makoto Kobayashi, Fukushima, JP;

Inventor:

Makoto Kobayashi, Fukushima, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provide a method for manufacturing an SOI wafer which suppresses voids from being generated in an SOI wafer, especially, in an outer peripheral portion thereof to achieve high productivity. According to the present invention, in a method for manufacturing an SOI wafer in which an insulating layer is formed on at least one of two wafers serving as starting wafers, and the wafer is bonded to the other wafer without an adhesive, a wafer having such an outer peripheral configuration that a configuration change width is 0.1 μm or less in a region of between 10 mm and 3 mm away from the outer periphery is used as the starting wafer.


Find Patent Forward Citations

Kobayashi, Makoto. (2008). Method for manufacturing soi wafer (U.S. Patent No. 7435662). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7435662

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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