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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7230680 B1

PDFFull Text
Date of Patent:
Jun. 12, 2007

Filed:

Dec. 19, 2003

Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method

Applicants:

Tadahito Fujisawa, Tokyo, JP;

Soichi Inoue, Yokohama, JP;

Makoto Kobayashi, Nishishirakawa-gun, JP;

Masashi Ichikawa, Nishishirakawa-gun, JP;

Tsuneyuki Hagiwara, Tokyo, JP;

Kenichi Kodama, Mito, JP;

Inventors:

Tadahito Fujisawa, Tokyo, JP;

Soichi Inoue, Yokohama, JP;

Makoto Kobayashi, Nishishirakawa-gun, JP;

Masashi Ichikawa, Nishishirakawa-gun, JP;

Tsuneyuki Hagiwara, Tokyo, JP;

Kenichi Kodama, Mito, JP;

Assignees:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Shin-Etsu Handotai Co., Ltd., Tokyo, JP;

Nikon Corporation, Tokyo, JP;

Attorney:

Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

Primary Examiner:

Peter B Kim

Int. Cl.
CPC ...
G03B 27/58 (2006.01); G03B 27/42 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

Find Patent Forward Citations

Fujisawa, Tadahito. (2007). Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method (U.S. Patent No. 7230680). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7230680

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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