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For the Inventor, By the Inventor

Santa Barbara, CA, United States of America

Kwang-Ting Cheng

This inventor holds 14 USPTO granted patents. Top assignees: Lucent Technologies Inc., Agere Systems Inc., At&t Bell Laboratories. Active years: 1991-2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kwang-Ting Cheng. Retrieved from https://idiyas.com/inventor/kwang-ting-cheng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 92.9

Average Co-Inventor Count = 2.4

ph-index = 10

Forward Citations = 374(Granted Patents)


Location History:

  • North Plainfield, NJ (US) (1991)
  • Edison, NJ (US) (1993 - 1998)
  • Santa Barbara, CA (US) (1996 - 2007)

Company Filing History:

goldMedal4 out of 9,364 
 
Lucent Technologies Inc.
 patents
silverMedal2 out of 2,316 
 
Agere Systems Inc.
 patents
bronzeMedal2 out of 3,345 
 
At&t Bell Laboratories
 patents
4. 2 out of 3 
 
Vima Technologies, Inc.
 patents
5. 1 out of 598 
 
Agere Systems Guardian Corp.
 patents
6. 1 out of 4,208 
 
At+t Corp.
 patents
7. 1 out of 94 
 
Nec USA, Inc.
 patents
8. 1 out of 834,513 
Other
 patents

Years Active: 1991-2007

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14 patents (USPTO):Explore Patents
1. 7158970 - Maximizing expected generalization for learning complex query concepts (2007-01-02),
2. 6976016 - Maximizing expected generalization for learning complex query concepts (2005-12-13),
3. 6694466 - Method and system for improving the test quality for scan-based BIST using a general test application scheme (2004-02-17),
4. 6463561 - Almost full-scan BIST method and system having higher fault coverage and shorter test application time (2002-10-08),
5. 6345373 - System and method for testing high speed VLSI devices using slower testers (2002-02-05),
6. 6256759 - Hybrid algorithm for test point selection for scan-based BIST (2001-07-03),
7. 6018813 - Identification and test generation for primitive faults (2000-01-25),
8. 5828828 - Method for inserting test points for full-and-partial-scan built-in (1998-10-27),
9. 5710711 - Method and integrated circuit adapted for partial scan testability (1998-01-20),
10. 5590135 - Testing a sequential circuit (1996-12-31),
11. 5587919 - Apparatus and method for logic optimization by redundancy addition and (1996-12-24),
12. 5513122 - Method and apparatus for determining the reachable states in a hybrid (1996-04-30),
13. 5228040 - Testable implementations of finite state machines and methods for (1993-07-13),
14. 5043986 - Method and integrated circuit adapted for partial scan testability (1991-08-27),

Title: The Innovative Journey of Kwang-Ting Cheng

Introduction: Kwang-Ting Cheng, a pioneering inventor based in Santa Barbara, CA, has made significant contributions to the field of technology and innovation.

Latest Patents: Kwang-Ting Cheng holds several patents in the areas of semiconductor technology, integrated circuits, and computer architecture, showcasing his expertise and creativity in these domains.

Career Highlights: With a distinguished career spanning several decades, Cheng has held key positions in leading tech companies and research institutions. His work has been instrumental in advancing the development of cutting-edge technologies.

Collaborations: Throughout his career, Kwang-Ting Cheng has collaborated with top researchers, engineers, and innovators in the industry, fostering a culture of innovation and excellence in all his projects.

Conclusion: Kwang-Ting Cheng's relentless pursuit of innovation and his groundbreaking inventions have left an indelible mark on the world of technology, inspiring future generations of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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