Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Inc.

Vima Technologies, Inc.

Other

At+t Corp.

Agere Systems Guardian Corp.

Nec Usa, Inc.

Kwang-Ting Cheng

Vishwani D Agrawal

Sudipta Bhawmik

Huan-Chih Tsai

Srimat T Chakradhar

Edward Y Chang

Angela Krstic

Chih-Jen Lin

Anjur Sundaresan Krishnakumar

Miron Abramovici

Krishna B Rajan

Luis Entrena

Jing-Yang Jou

A method of learning a user query concept is provided which includes a sample selection stage and a feature reduction stage; during the sample selection stage, sample objects are selected from a query concept sample space bounded by a k-CNF and a k-DNF; the selected sample objects include feature sets that are no more than a prescribed amount different from a corresponding feature set defined by the k-CNF; during the feature reduction stage, individual features are removed from the k-CNF that are identified as differing from corresponding individual features of sample objects indicated by the user to be close to the user's query concept; also during the feature reduction stage, individual features are removed from the k-DNF that are identified as not differing from corresponding individual features of sample objects indicated by the user to be not close to the user's query concept.

Maximizing expected generalization for learning complex query concepts

A method of learning user query concept for searching visual images encoded in computer readable storage media comprising: providing a multiplicity of sample images encoded in a computer readable medium; providing a multiplicity of sample expressions that correspond to sample images and in which terms of the sample expressions represent features of corresponding sample images; defining a user query concept sample space bounded by a boundary k-CNF expression and by a boundary k-DNF expression refining the user query concept sample space by, soliciting user feedback as to which of the multiple presented sample images are close to the user's query concept; removing from the boundary k-CNF expression disjunctive terms based upon the solicited user feedback; and removing from the boundary k-DNF expression respective conjunctive terms based upon the solicited user feedback.

A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.

Method and system for improving the test quality for scan-based BIST using a general test application scheme

An almost full-scan method and system for detecting faults in circuits can achieve higher fault coverages and significantly shorter test application time as compared with full-scan techniques. A special flip-flop selection of strategy is further described which permits implementation of the almost full-scan BIST method and system.

Almost full-scan BIST method and system having higher fault coverage and shorter test application time

At-speed strategies for testing high speed designs on slower testers. At-speed testing schemes is provided that integrates the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. A slow tester that uses test vectors that are generated while taking into account the speed of the tester.

System and method for testing high speed VLSI devices using slower testers

A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.

Hybrid algorithm for test point selection for scan-based BIST

A method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault will degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). The methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) reduce or prune the combination of paths that can never belong to any primitive fault. The procedure for identifying a primitive fault also produces a test for the fault. A complete algorithm is presented for identifying and testing double path delay faults. A similar procedure can be used to identify primitive faults consisting of three or more paths. Experimental results on several multi-level combinational benchmark circuits are included to demonstrate the usefulness and efficiency of the technique.

Identification and test generation for primitive faults

Test points (20, 24) placed at selected nodes (16) within a circuit (10) based on a cost function that accounts for (a) the global improvement in testability and (b) the penalty in circuit performance associated with propagation delays attributable to such test points. By accounting for both the global impact on testability and circuit performance degradation, the cost function maximizes fault coverage while achieving nearly minimal impairment of circuit performance.

Method for inserting test points for full-and-partial-scan built-in

A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memory elements in a circuit based on their ability to eliminate feedback cycles in the circuit and on considerations of the potential performance degradation due to the inclusion of scan memory elements. A feedback cycle is defined as a feedback path from the output of a memory element to the input of said memory element.

Method and integrated circuit adapted for partial scan testability

A method for testing a sequential circuit by applying a number of test vectors to the primary inputs of the sequential circuit between each application of a clock circuit. Once the sequential circuit enters a state and that state is a necessary condition for detecting various faults, test vectors are applied to the primary inputs of the sequential circuit, which vectors are designed to propagate all fault effects that can be propagated at that state of the circuit. Once those vectors have been applied, a state-advancing vector is applied immediately before the application of the clock. The state-advancing vector is designed to condition the circuit to allow more fault effects to be propagated to the primary outputs, and to propagate fault effects into the storage elements of the circuit.

Testing a sequential circuit

A method is disclosed for optimizing a digital logic network through the iterative addition and removal of redundant connections. Redundancy testing is performed on connections absolutely dominated by the node of the network being optimized to find redundant connections and connections that can be added to the network which would create more redundant connections elsewhere in the network which may under appropriate conditions be removed to simplify the network. Application of the redundancy addition and removal network optimization technique to selected connections in a network improves the cost efficiency of network optimization because a network is optimized by the consideration of a reduced number of candidate connections for addition.

Apparatus and method for logic optimization by redundancy addition and

The present invention provides a method and apparatus for more efficiently validating high-level specifications of sequential digital systems, and in particular, those represented by hybrid models. According to the present invention, the high-level representation of a system is converted into a direct sum EFSM. An operator or a data file then provides an initial configuration or set of initial configurations of states and variable values. The method of the present invention then determines the set of configuration reachable from the initial configuration through symbolic execution of the direct sum EFSM. By representing the transitional relations of the machine as the and-product of Boolean expressions and arithmetic expressions, each class of expressions may be processed separately. When complete, the symbolic execution produces a cover of the set of reachable states. The results may then be reviewed to determine if the given specification produces unexpected or incompatible results.

Method and apparatus for determining the reachable states in a hybrid

A testable implementation of a given finite state machine is produced by defining a test finite state machine which can set and read the same number of flip flops as are required for the memory elements of the given finite machine and then merging the test finite state machine with the given finite state machine to produce a testable finite state machine in which the test finite state machine and the given finite state machine share the flip flops. The testable implementation is then produced from the testable finite state machine. Since the test finite state machine and the given finite state machine share the flip flops of the testable implementation, the test finite state machine can be used to test the given finite state machine by setting and reading the given finite state machine's flip flops. Techniques are further disclosed for defining the test finite state machine and merging the test finite state machine with the given finite state machine.

Testable implementations of finite state machines and methods for

A method of partial scan design for chip testing and a circuit produced in accordance with the method in which the selection of scan memory elements eliminates cycles in the circuit while the circuit is in a test mode. Cycles are defined as feedback paths from an output of a memory element to an input of the memory element. Cycle length is the number of memory elements in a feedback path. Experimental data suggests that test complexity grows exponentially with the cycle length. By eliminating cycles of desired lengths, the set of scan memory elements may be only a small fraction of the total memory elements of a circuit.

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Santa Barbara, CA, United States of America

Kwang-Ting Cheng