The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 1996

Filed:

Apr. 22, 1994
Applicant:
Inventors:

Kwang-Ting Cheng, Santa Barbara, CA (US);

Luis Entrena, Madrid, ES;

Assignee:

Lucent Technologies, Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364489 ; 364488 ;
Abstract

A method is disclosed for optimizing a digital logic network through the iterative addition and removal of redundant connections. Redundancy testing is performed on connections absolutely dominated by the node of the network being optimized to find redundant connections and connections that can be added to the network which would create more redundant connections elsewhere in the network which may under appropriate conditions be removed to simplify the network. Application of the redundancy addition and removal network optimization technique to selected connections in a network improves the cost efficiency of network optimization because a network is optimized by the consideration of a reduced number of candidate connections for addition.


Find Patent Forward Citations

Cheng, Kwang-Ting. (1996). Apparatus and method for logic optimization by redundancy addition and (U.S. Patent No. 5587919). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5587919

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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