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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Konstantine N Karavakis

This inventor holds 74 USPTO granted patents and 8 published patent applications and 3 EPO patents, primarily in Printed Circuit Boards (CPC class H05K). Top assignees: Adeia Semiconductor Bonding Technologies Inc., Catlam, LLC, Sierra Circuits, Inc.. Active years: 1997-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Konstantine N Karavakis. Retrieved from https://idiyas.com/inventor/konstantine-n-karavakis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 74 

% Patents Active = 82.4

 

Average Co-Inventor Count = 2.4

ph-index = 22

Forward Citations = 1,849(Granted Patents)

Forward Citations (Not Self Cited) = 1,782(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Coram, NY (US) (1997)
  • Cupertino, CA (US) (1997 - 2003)
  • Pleasant Hill, CA (US) (2003 - 2005)
  • Livermore, CA (US) (2020)
  • Pleasanton, CA (US) (1999 - 2023)

Company Filing History:

goldMedal44 out of 1,908 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
silverMedal13 out of 15 
 
Catlam, LLC
 patents
bronzeMedal9 out of 9 
 
Sierra Circuits, Inc.
 patents
4. 4 out of 8 
 
Celerity Research Pte. Ltd.
 patents
5. 4 out of 40 
 
Centipede Systems, Inc.
 patents

Years Active: 1997-2025

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Areas of Expertise:
Catalytic Laminate
Conductive Traces
Printed Circuit Board
Interposer Layer
Compliant Layers
Microelectronic Assemblies
Electroless Deposition
Semi-Additive Process
Thermal Contactor
Wafer Level Packaging
Testing Circuits
Integrated Circuit
74 patents (USPTO):Explore Patents
1. 12513827 - Semi-additive process for catalytic printed circuit boards (2025-12-30),
2. 11653453 - Electroless and electrolytic deposition process for forming traces on a catalytic laminate (2023-05-16),
3. 11638354 - Process for fabrication of a printed circuit board using a semi-additive process and removable backing foil (2023-04-25),
4. 11477893 - Catalytic laminate with conductive traces formed during lamination (2022-10-18),
5. 10959329 - Circuit board using non-catalytic laminate with catalytic adhesive overlay (2021-03-23),
6. 10849233 - Process for forming traces on a catalytic laminate (2020-11-24),
7. 10827624 - Catalytic laminate with conductive traces formed during lamination (2020-11-03),
8. 10806029 - Catalytic circuit board with traces and vias (2020-10-13),
9. 10765012 - Process for printed circuit boards using backing foil (2020-09-01),
10. 10765003 - Method for making a multi-layer circuit board using conductive paste with interposer layer (2020-09-01),
11. 10685931 - Method and apparatus for forming contacts on an integrated circuit die using a catalytic adhesive (2020-06-16),
12. 10573610 - Method for wafer level packaging (2020-02-25),
13. 10349520 - Multi-layer circuit board using interposer layer and conductive paste (2019-07-09),
14. 10306756 - Circuit board with catalytic adhesive (2019-05-28),
15. 9942981 - Circuit board apparatus and method (2018-04-10),

Title: Konstantine N Karavakis: Pioneering Inventor from Cupertino

Introduction: Konstantine N Karavakis is a renowned inventor based in Cupertino, California, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Karavakis holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Karavakis has worked with leading tech companies, spearheading research and development projects that have led to significant technological breakthroughs.

Collaborations: Throughout his career, Karavakis has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and creativity that has resulted in numerous successful projects and inventions.

Conclusion: Konstantine N Karavakis continues to inspire the next generation of inventors and innovators with his visionary work and dedication to shaping the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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