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For the Inventor, By the Inventor

Nishishirakawa, Japan

Koichi Kanaya

This inventor holds 9 USPTO granted patents and 3 EPO patents. Top assignees: Shin-Etsu Handotai Co., Ltd., Japan Ade. Ltd.. Active years: 1996-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Koichi Kanaya. Retrieved from https://idiyas.com/inventor/koichi-kanaya-d0ljdwv6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 9

% Patents Active = 88.9


Average Co-Inventor Count = 2.3

ph-index = 4

Forward Citations = 92(Granted Patents)


Location History:

  • Annaka, JP (1996 - 2001)
  • Gunma, JP (2005 - 2008)
  • Nishishirakawa-gun, JP (2009)
  • Fukushima, JP (2010)
  • Tokyo, JP (2012)
  • Nishigo-mura, JP (2022)

Company Filing History:

goldMedal9 out of 1,099 
 
Shin-Etsu Handotai Co., Ltd.
 patents
silverMedal1 out of 1 
 
Japan Ade. Ltd.
 patent
where one patent can have more than one assignee

Years Active: 1996-2022

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9 patents (USPTO):Explore Patents
1. 11486833 - Method for evaluating edge shape of silicon wafer, apparatus for evaluating thereof, silicon wafer, method for selecting and method for manufacturing thereof (2022-11-01),
2. 8287331 - Method for manufacturing polishing pad, and method for polishing wafer (2012-10-16),
3. 7779554 - Holding gripper and holding method for semiconductor wafer and shape measuring apparatus (2010-08-24),
4. 7615116 - Method for producing silicon epitaxial wafer and silicon epitaxial wafer (2009-11-10),
5. 7591908 - Vapor deposition apparatus and vapor deposition method (2009-09-22),
6. 7459720 - Single crystal wafer and solar battery cell (2008-12-02),
7. 6958094 - Single crystal cutting method (2005-10-25),
8. 6217651 - Method for correction of thin film growth temperature (2001-04-17),
9. 5571333 - Heat treatment furnace with an exhaust baffle (1996-11-05),

Title: Innovations by Koichi Kanaya

Introduction

Koichi Kanaya is a notable inventor based in Nishishirakawa-gun, Japan. He has made significant contributions to the field of silicon wafer technology, holding a total of 9 patents. His work focuses on methods and apparatuses that enhance the evaluation and manufacturing processes of silicon wafers.

Latest Patents

Among his latest patents, Kanaya has developed a method for evaluating the edge shape of silicon wafers. This method involves defining specific shape parameters in a wafer cross-section, allowing for precise measurements of the edge shape. By calculating values based on measurement data, the method effectively prevents potential issues during wafer production. Additionally, he has patented a method for manufacturing polishing pads, which are essential for achieving high flatness in wafers. This method includes slicing urethane foam and applying significant pressure during processing to ensure quality.

Career Highlights

Throughout his career, Koichi Kanaya has worked with prominent companies such as Shin-Etsu Handotai Co., Ltd. and Japan Ade Ltd. His experience in these organizations has contributed to his expertise in silicon wafer technology and innovation.

Collaborations

Kanaya has collaborated with notable colleagues, including Tadahiro Ohmi and Shigetoshi Sugawa. Their combined efforts have further advanced the field of silicon wafer evaluation and manufacturing.

Conclusion

Koichi Kanaya's contributions to silicon wafer technology through his innovative patents and collaborations highlight his importance in the field. His work continues to influence the industry, ensuring advancements in wafer production and quality.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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