Kiyohito Mukai

USPTO Granted Patents = 11 (Patent Applications = 1)

Average Co-Inventor Count = 2.2

ph-index = 7

Forward Citations = 99(Granted Patents)

Location History:

Habikino, JP (2001)
Takatsuki, JP (2002 - 2007)
Souraku-gun, JP (2007)
Osaka, JP (2006 - 2010)
Kyoto, JP (2007 - 2011)

Company Filing History:

9 out of 27,375

Matsushita Electric Industrial Co., Ltd.

patents

2 out of 16,453

Panasonic Corporation

patents

Years Active: 2001-2011

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11 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8024689 - Semiconductor integrated circuit apparatus with low wiring resistance (2011-09-20),

2. 7707523 - Method of fabricating a semiconductor device and a method of generating a mask pattern (2010-04-27),

3. 7269807 - Area ratio/occupancy ratio verification method and pattern generation method (2007-09-11),

4. 7174527 - Layout verification method and method for designing semiconductor integrated circuit device using the same (2007-02-06),

5. 7171645 - Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device (2007-01-30),

6. 7115478 - Method of fabricating a semiconductor device and a method of generating a mask pattern (2006-10-03),

7. 7062732 - Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device (2006-06-13),

8. 6576147 - Method of layout compaction (2003-06-10),

9. 6473882 - Method of layout compaction (2002-10-29),

10. 6303251 - Mask pattern correction process, photomask and semiconductor integrated circuit device (2001-10-16),

11. 6183920 - Semiconductor device geometrical pattern correction process and geometrical pattern extraction process (2001-02-06),

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1 patent pending:

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