Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kiyohito Mukai

Mitsumi Ito

Hiroyuki Tsujikawa

Junichi Shimada

Hidenori Shibata

Tadashi Tanimoto

Fumihiro Kimura

Noriko Shinomiya

Masanori Itou

It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

Semiconductor integrated circuit apparatus with low wiring resistance

At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.

Method of fabricating a semiconductor device and a method of generating a mask pattern

Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.

Area ratio/occupancy ratio verification method and pattern generation method

To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification method according to the invention is characterized in that an antenna value which is an estimated value of transistor gate damage is output based on an antenna ratio, and a fluctuation of plasma charging damage due to the layout near the transistor gate.

Layout verification method and method for designing semiconductor integrated circuit device using the same

To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high. A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device

To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized. Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device

It is an object of the invention to carry out layout compaction in which optical proximity effect is taken account of the irregularly disposed layout patterns also contained within circuit design data to increase the degree of integration of the semiconductor integrated circuit devices. A compaction control step generates a compaction condition; an optical proximity correction condition generation step generates an optical proximity correction information; a layout compaction step compacts an input layout pattern; an optical proximity correction step corrects an optical proximity effect: a corrected layout pattern retention step retains an optical proximity corrected layout pattern; a verification step verifies circuit operation on compacted and optical proximity corrected layout patterns; an error data retention step retains a layout pattern having any problem; the compaction control step generates a compaction condition again in which optical proximity effect and error data are taken account of; and the above-mentioned steps are repeated.

Method of layout compaction

In order that CAD processing time required for modifying an input design pattern to compensate for optical proximity effects is reduced, increases in the number of base shapes when corrected data are converted into EB data are restricted, and false detection of defects in a photomask inspection process is restricted, the following steps are taken. At a shape selection step, rectangular shapes are divided into a dense rectangular shape group and a non-dense rectangular shape group according to the distance of each rectangular shape to an adjacent rectangular shape. At a number-of-shapeas comparison step, the number of shapes included in the dense rectangular shape group is compared to the number of shapes included in the non-dense rectangular shape group to select either shape group for correction. At a correction process selection step, a correction process suited for the selected shape group is selected. At a shape correction step, optical proximity correction is made. At a shape combining step, a group of corrected shapes and the rectangular shape group different from the selected one are combined.

Mask pattern correction process, photomask and semiconductor integrated circuit device

A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step,of detecting a concave diffusion layer corresponding portion and a step,of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.

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Kyoto, Japan

Kiyohito Mukai