The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2002
Filed:
Apr. 02, 2001
Kiyohito Mukai, Takatsuki, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
It is an object of the invention to carry out layout compaction in which optical proximity effect is taken account of the irregularly disposed layout patterns also contained within circuit design data to increase the degree of integration of the semiconductor integrated circuit devices. A compaction control step generates a compaction condition; an optical proximity correction condition generation step generates an optical proximity correction information; a layout compaction step compacts an input layout pattern; an optical proximity correction step corrects an optical proximity effect: a corrected layout pattern retention step retains an optical proximity corrected layout pattern; a verification step verifies circuit operation on compacted and optical proximity corrected layout patterns; an error data retention step retains a layout pattern having any problem; the compaction control step generates a compaction condition again in which optical proximity effect and error data are taken account of; and the above-mentioned steps are repeated.