Santa Clara, CA, United States of America

Kevin J Yang

This inventor holds 18 USPTO granted patents, primarily in Thyristor Technology. Top assignees: T-Ram Semiconductor, Inc., Globalfoundries Inc.. Active years: 2006-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kevin J Yang. Retrieved from https://idiyas.com/inventor/kevin-j-yang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 18

% Patents Active = 5.6

Average Co-Inventor Count = 2.5

ph-index = 8

Forward Citations = 504(Granted Patents)

Company Filing History:

16 out of 58

T-Ram Semiconductor, Inc.

Years Active: 2006-2015

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Areas of Expertise:

Integrated Circuits

Thyristor Memory

Memory Cells

Fabrication Methods

Electrostatic Coupling

Charge Leakage

Performance Modeling

Silicide Uniformity

Parasitic Transistors

Lifetime Adjustment

Isolation Regions

Semiconductor Devices

18 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8940608 - Methods for fabricating integrated circuits with drift regions and replacement gates (2015-01-27),

2. 8352895 - Model library implementation and methodology for worst case performance modeling for SRAM cells (2013-01-08),

3. 8324656 - Reduction of electrostatic coupling for a thyristor-based memory cell (2012-12-04),

4. 8093107 - Thyristor semiconductor memory and method of manufacture (2012-01-10),

5. 7894256 - Thyristor based memory cell (2011-02-22),

6. 7894255 - Thyristor based memory cell (2011-02-22),

7. 7893456 - Thyristor-based memory and its method of operation (2011-02-22),

8. 7858449 - Thyristor device with carbon lifetime adjustment implant and its method of fabrication (2010-12-28),

9. 7786505 - Reduction of charge leakage from a thyristor-based memory cell (2010-08-31),

10. 7554130 - Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region (2009-06-30),

11. 7491586 - Semiconductor device with leakage implant and method of fabrication (2009-02-17),

12. 7488627 - Thyristor-based memory and its method of operation (2009-02-10),

13. 7488626 - Thyristor device with carbon lifetime adjustment implant and its method of fabrication (2009-02-10),

14. 7381999 - Workfunction-adjusted thyristor-based memory device (2008-06-03),

15. 7262443 - Silicide uniformity for lateral bipolar transistors (2007-08-28),

Title: Profile of Kevin J Yang: Innovator in Integrated Circuit Technologies

Introduction

Kevin J Yang, based in Santa Clara, CA, is a prominent inventor with a remarkable portfolio of 18 patents. His contributions to the field of integrated circuits and semiconductor technologies are notable, reflecting his commitment to innovation and excellence.

Latest Patents

Among his latest patents, two significant inventions stand out. The first is related to methods for fabricating integrated circuits with drift regions and replacement gates. This method involves a semiconductor substrate with a strategically positioned drift region, enhancing the efficiency of source/drain ion implantation. The second patent focuses on a model library implementation and methodology for worst-case performance modeling of SRAM cells. This invention optimizes the simulation of worst-case performance, improving accuracy while reducing computation resources.

Career Highlights

Kevin has made significant strides in his career through his work with companies like T-RAM Semiconductor, Inc. and Globalfoundries Inc. His expertise has propelled advancements in semiconductor technologies and circuit design, establishing him as a leader in his field.

Collaborations

During his career, Kevin has collaborated with esteemed professionals such as Farid Nemati and Scott T Robins. These collaborations have further enriched his work, cultivating innovations that push the boundaries of technology.

Conclusion

Kevin J Yang stands as a notable inventor whose patents and innovations have considerably impacted integrated circuit fabrication and performance modeling. His career reflects a dedication to enhancing semiconductor technologies and driving innovation in the industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]