T-ram Semiconductor, Inc.

Globalfoundries Inc.

Kevin J Yang

Farid Nemati

Scott T Robins

Hyun-Jin Cho

James D Plummer

Rajesh N Gupta

Andrew Edward Horch

Marc Laurent Tarabbia

Jia Feng

Zhi-Yuan Wu

Zachary K Lee

Kuldeep Amarnath

Sriram Balasubramanian

Lingquan Wang

Juhi Bansal

Karthik Chandrasekaran

Vineet Wason

Varsha Balakrishnan

Arunima Dasgupta

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Methods for fabricating integrated circuits with drift regions and replacement gates

Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Ibased on the local Monte Carlo simulations around process corner G, extrapolating the worst case Ifrom the normal probability distribution of Ito define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner. Embodiments further include creating a library of SRM corner values for multiple SRAM cells, and validating an SRAM cell by selecting an SRM corner from the library. Embodiments further include linearly scaling the SRM corner value with global sigma input variations from 0 sigma to 6 sigma and/or with local sigma input variations from 0 sigma to 6 sigma, selecting a scaled SRM corner value at the sigma corresponding to design and memory size requirements for the SRAM cell, simulating the scaled SRM corner by a processor, and employing the simulated scaled SRM corner to validate performance of an SRAM cell.

Model library implementation and methodology for worst case performance modeling for SRAM cells

Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.

Reduction of electrostatic coupling for a thyristor-based memory cell

A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted 'T' shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted 'T' shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.

Thyristor semiconductor memory and method of manufacture

A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Thyristor based memory cell

A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

Thyristor-based memory and its method of operation

In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Thyristor device with carbon lifetime adjustment implant and its method of fabrication

Formation of a thyristor-based memory cell is described. A first gate dielectric of the storage element is formed over a base region thereof located in a silicon layer. A transistor is coupled to the storage element via a cathode region located in the silicon layer. The transistor has a gate electrode formed over a second gate dielectric. A spacer is formed at least in part along a sidewall of the gate electrode facing a gate electrode of the storage element. A shallow implant region is formed in the silicon layer responsive at least in part to the spacer. The spacer offsets the shallow implant region from the sidewall. A portion of the shallow implant region is for an extension region. The first gate dielectric and the second gate dielectric are formed at least in part by deposition of a dielectric material.

Reduction of charge leakage from a thyristor-based memory cell

An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.

Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region

A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Semiconductor device with leakage implant and method of fabrication

A memory device having a thyristor-based storage element and an access device coupled to the thyristor-based storage element at a common storage node is described. The thyristor-based storage element has a first gate stack, where the first gate stack has a first workfunction configured to a base region of the thyristor-based storage element. The access device has a second gate stack, where the second gate stack has a second workfunction. The first gate stack includes a first conductive layer formed over a gate dielectric and a second conductive layer formed over the first conductive layer. The second gate stack includes the second conductive layer formed over the gate dielectric. The first workfunction is operationally distinct from the second workfunction.

Workfunction-adjusted thyristor-based memory device

Method and apparatus for forming a semiconductor device. The method includes defining a plurality of rows in a semiconductor layer. Thereafter, on one or more of the plurality of rows, one or more bipolar junction devices are formed. Each of the bipolar junction devices has a first end region and a second end region. A quantity of a pre-amorphization ion is then implanted into at least one of the first end region and the second end region of a bipolar junction device for example. A silicide is formed in the semiconductor layer at the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion. Additionally, laterally extending upper edges of the plurality of rows forming corners may be rounded prior to the implantation of the pre-amorphization.

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Santa Clara, CA, United States of America

Kevin J Yang