Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region

Abstract

An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.