IDiyas

For the Inventor, By the Inventor

Ghaziabad, India

Kedar Janardan Dhori

USPTO Granted Patents = 24 

 

Average Co-Inventor Count = 3.4

ph-index = 3

Forward Citations = 13(Granted Patents)


Company Filing History:

goldMedal24 out of 972 
 
Stmicroelectronics International N.v.
 patents
silverMedal2 out of 5,553 
 
Stmicroelectronics S.r.l.
 patents
bronzeMedal1 out of 37 
 
Stmicroelectronics France
 patents
4. 1 out of 757 
 
Stmicroelectronics (crolles 2) Sas
 patents
where one patent can have more than one assignee

Years Active: 2015-2025

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24 patents (USPTO):
1. 12482518 - Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current (2025-11-25),
2. 12469545 - Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-11-11),
3. 12437825 - At-speed transition fault testing for a multi-port and multi-clock memory (2025-10-07),
4. 12406705 - In-memory computation circuit using static random access memory (SRAM) array segmentation (2025-09-02),
5. 12400707 - Device and method for reading data from memory cells (2025-08-26),
6. 12361982 - Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode (2025-07-15),
7. 12354644 - Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-07-08),
8. 12353341 - Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection (2025-07-08),
9. 12328858 - Silicon-on-insulator semiconductor device with a static random access memory circuit (2025-06-10),
10. 12292780 - Computing system power management device, system and method (2025-05-06),
11. 12237007 - Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-02-25),
12. 12183424 - Bit-cell architecture based in-memory compute (2024-12-31),
13. 12176025 - Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2024-12-24),
14. 12170120 - Built-in self test circuit for segmented static random access memory (SRAM) array input/output (2024-12-17),
15. 12165698 - Circuitry for adjusting retention voltage of a static random access memory (SRAM) (2024-12-10),

Title: Kedar Janardan Dhori: A Pioneer in Memory Architecture Innovations

Introduction

Kedar Janardan Dhori, based in Ghaziabad, India, is an accomplished inventor with a remarkable portfolio of 19 patents. His innovations primarily focus on advanced memory architecture, catering to both conventional memory access modes and digital in-memory computation processing modes. His contributions are shaping the future of computing and memory technology.

Latest Patents

Among his latest patents are groundbreaking designs that enhance memory architecture. One notable invention is a memory architecture that supports both traditional memory access and digital in-memory computation. This innovation involves a circuit with memory cells arranged in a row-column matrix. The design allows a control circuit to operate in two modes, enabling efficient memory reads by actuation of word lines in various configurations.

Another significant patent by Dhori is the development of an adaptive word line underdrive control for in-memory compute operations. This circuit utilizes SRAM cells organized by word and bit lines, where a row controller simultaneously actuates these word lines for optimized in-memory computation. The adaptive supply voltage generated for powering these circuits enhances performance, particularly by minimizing unwanted memory cell data flips, crucial for maintaining data integrity during processing.

Career Highlights

Kedar Dhori's career features impressive collaborations with leading companies in the technology sector. He has worked extensively with STMicroelectronics, a global leader in semiconductor solutions. His contributions within the company have paved the way for advancements in memory technologies.

Collaborations

Throughout his career, Dhori has collaborated with talented professionals such as Nitin Chawla and Manuj Ayodhyawasi. These partnerships have fostered innovation and supported the development of cutting-edge memory architectures, further establishing Dhori's reputation within the industry.

Conclusion

Kedar Janardan Dhori stands out as a notable inventor in the field of memory architecture. With his impressive patent portfolio and significant contributions to memory technology, he continues to influence the research and development landscape. As the demand for advanced computing solutions grows, Dhori's innovations are sure to play a pivotal role in shaping the future of technology.

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