The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Apr. 20, 2023
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Kedar Janardan Dhori, Ghaziabad, IN;

Nitin Chawla, Noida, IN;

Promod Kumar, Greater Noida, IN;

Harsh Rawat, Faridabad, IN;

Manuj Ayodhyawasi, Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/419 (2006.01); G11C 11/54 (2006.01); G06N 3/065 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 7/1006 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/419 (2013.01); G11C 11/54 (2013.01); G06N 3/065 (2023.01);
Abstract

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.


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