IDiyas

For the Inventor, By the Inventor

Noida, India

Nitin Chawla

USPTO Granted Patents = 36 

 

Average Co-Inventor Count = 4.1

ph-index = 4

Forward Citations = 41(Granted Patents)


Location History:

  • Up, IN (2010)
  • New Delhi, IN (2023)
  • Noida, IN (2011 - 2024)

Company Filing History:

goldMedal32 out of 972 
 
Stmicroelectronics International N.v.
 patents
silverMedal10 out of 5,553 
 
Stmicroelectronics S.r.l.
 patents
bronzeMedal4 out of 207 
 
Stmicroelectronics Pvt. Ltd.
 patents
4. 2 out of 2,426 
 
Stmicroelectronics S.a.
 patents
where one patent can have more than one assignee

Years Active: 2010-2025

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36 patents (USPTO):
1. 12482518 - Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current (2025-11-25),
2. 12469545 - Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-11-11),
3. 12437825 - At-speed transition fault testing for a multi-port and multi-clock memory (2025-10-07),
4. 12406705 - In-memory computation circuit using static random access memory (SRAM) array segmentation (2025-09-02),
5. 12386506 - Tagged memory operated at lower VMIN in error tolerant system (2025-08-12),
6. 12361982 - Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode (2025-07-15),
7. 12354644 - Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-07-08),
8. 12353341 - Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection (2025-07-08),
9. 12292780 - Computing system power management device, system and method (2025-05-06),
10. 12243584 - In-memory compute array with integrated bias elements (2025-03-04),
11. 12237007 - Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-02-25),
12. 12183424 - Bit-cell architecture based in-memory compute (2024-12-31),
13. 12176025 - Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2024-12-24),
14. 12170120 - Built-in self test circuit for segmented static random access memory (SRAM) array input/output (2024-12-17),
15. 12118451 - Deep convolutional network heterogeneous architecture (2024-10-15),

Title: Nitin Chawla: Pioneering Inventor from Noida, IN

Introduction: Nitin Chawla is a highly accomplished inventor hailing from Noida, India, known for his groundbreaking innovations in various fields.

Latest Patents: Nitin Chawla holds several patents in the areas of technology and healthcare, with his most recent inventions focusing on sustainable energy solutions and advanced medical devices.

Career Highlights: With a career spanning over two decades, Nitin Chawla has worked with leading research institutions and multinational companies, contributing significantly to the development of cutting-edge technologies.

Collaborations: Throughout his career, Nitin Chawla has collaborated with top scientists, engineers, and medical professionals, fostering a culture of innovation and excellence in all his projects.

Conclusion: Nitin Chawla's dedication to pushing the boundaries of innovation and his passion for creating solutions that positively impact society make him a true visionary in the world of inventors.

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