The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2025
Filed:
Oct. 12, 2023
Stmicroelectronics International N.v., Geneva, CH;
Bhupender Singh, New Delhi, IN;
Hitesh Chawla, Noida, IN;
Tanuj Kumar, Noida, IN;
Harsh Rawat, Faridabad, IN;
Kedar Janardan Dhori, Ghaziabad, IN;
Promod Kumar, Greater Noida, IN;
Manuj Ayodhyawasi, Noida, IN;
Nitin Chawla, Noida, IN;
STMicroelectronics International N.V., Geneva, CH;
Abstract
A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.