IDiyas

For the Inventor, By the Inventor

Haryana, India

Harsh Rawat

USPTO Granted Patents = 26 

 

Average Co-Inventor Count = 3.4

ph-index = 2

Forward Citations = 21(Granted Patents)


Location History:

  • Haryana, IN (2012 - 2024)
  • Faridabad, IN (2015 - 2024)

Company Filing History:

goldMedal25 out of 972 
 
Stmicroelectronics International N.v.
 patents
silverMedal1 out of 207 
 
Stmicroelectronics Pvt. Ltd.
 patents
bronzeMedal1 out of 757 
 
Stmicroelectronics (crolles 2) Sas
 patents
where one patent can have more than one assignee

Years Active: 2012-2025

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26 patents (USPTO):
1. 12482518 - Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current (2025-11-25),
2. 12469545 - Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-11-11),
3. 12437825 - At-speed transition fault testing for a multi-port and multi-clock memory (2025-10-07),
4. 12406705 - In-memory computation circuit using static random access memory (SRAM) array segmentation (2025-09-02),
5. 12361982 - Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode (2025-07-15),
6. 12354644 - Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-07-08),
7. 12353341 - Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection (2025-07-08),
8. 12340099 - Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion (2025-06-24),
9. 12237007 - Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2025-02-25),
10. 12183424 - Bit-cell architecture based in-memory compute (2024-12-31),
11. 12176025 - Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2024-12-24),
12. 12170120 - Built-in self test circuit for segmented static random access memory (SRAM) array input/output (2024-12-17),
13. 12159689 - SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications (2024-12-03),
14. 12087356 - Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) (2024-09-10),
15. 12068026 - Low power and fast memory reset (2024-08-20),

Title: The Innovative Mind of Harsh Rawat

Introduction

Harsh Rawat, an accomplished inventor from Haryana, India, has made significant contributions to the field of memory technology with a total of 21 patents to his name. His work focuses on advanced memory circuits, optimizing performance through innovative designs that cater to the needs of in-memory compute operations.

Latest Patents

Among his latest patents is the "Adaptive word line underdrive control for an in-memory compute operation". This invention discusses a sophisticated in-memory computation circuit comprising a memory array with Static Random Access Memory (SRAM) cells. Each row of the array features a word line drive circuit powered by an adaptive supply voltage. The row controller circuit allows for the simultaneous actuation of multiple word lines, enhancing efficiency during computations. Additionally, a voltage generator circuit modulates the adaptive supply voltage to optimize performance while preventing data flips in memory cells.

Another notable patent is titled "Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection". This patent describes a memory circuit with an array of cells arranged in a grid formation, operated through a control circuit that adjusts the read/write cycle timings based on selected operational modes. The circuit features dual delay mechanisms to efficiently manage the output signals for enhanced operational performance.

Career Highlights

Harsh Rawat has garnered significant experience working with prominent technology firms, particularly STMicroelectronics International N.V. and STMicroelectronics Pvt. Ltd. During his tenure at these companies, he has been integral in developing innovative solutions in semiconductor technology, driving research efforts and product development.

Collaborations

Throughout his career, Harsh has collaborated with several skilled professionals, including Kedar Janardan Dhori and Promod Kumar. These collaborations have undoubtedly contributed to the enriching of his inventive ideas and the successful execution of various projects.

Conclusion

Harsh Rawat stands out as a pioneering inventor in his field. His dedication to innovation is exemplified through his patents, which reflect a strong commitment to advancing memory technology. As he continues to explore new avenues for improvement, Harsh remains a crucial figure in the realm of semiconductor research and development.

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