The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Apr. 15, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Praveen Kumar Verma, Greater Noida, IN;

Christophe Lecocq, Varces, FR;

Yagnesh Dineshbhai Vaderiya, Greater Noida, IN;

Anuj Dhillon, New Delhi, IN;

Cedric Escallier, Seyssinet, FR;

Harsh Rawat, Faridabad, IN;

Kedar Janardan Dhori, Ghaziabad, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/32 (2006.01); G11C 29/02 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G11C 29/022 (2013.01); G11C 29/32 (2013.01); G11C 2029/3202 (2013.01);
Abstract

A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.


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