Noida, India

Manuj Ayodhyawasi

This inventor holds 22 USPTO granted patents and 21 published patent applications and 5 EPO patents, primarily in In-Memory Computing. Top assignees: Stmicroelectronics International N.v., Stmicroelectronics S.r.l.. Active years: 2022-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Manuj Ayodhyawasi. Retrieved from https://idiyas.com/inventor/manuj-ayodhyawasi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 100.0

 

Average Co-Inventor Count = 5.5

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2022-2026

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Areas of Expertise:
In-Memory Computing
SRAM Architecture
Bit Line Readout
Memory Circuit
Adaptive Control
Error Tolerance
Voltage Clamping
Self Test Circuit
Segmentation
Read Current
Cycle Time Delay
Neural Network Processors
22 patents (USPTO):Explore Patents

Title: The Innovative Mind of Manuj Ayodhyawasi

Introduction

Manuj Ayodhyawasi is a prominent inventor based in Noida, India. He has made significant contributions to the field of memory circuits and in-memory computation. With a total of 15 patents to his name, Ayodhyawasi continues to push the boundaries of technology and innovation.

Latest Patents

Among his latest patents is the invention titled "At-speed transition fault testing for a multi-port and multi-clock memory." This innovative memory circuit includes an address port, a data input port, and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port and input data to the data input port. Additionally, a downstream shadow logic circuit receives output data from the data output port. The memory circuit features a bypass path between the address port and the data output port, which is activated during testing operations to pass bits of address data as test data.

Another notable patent is the "In-memory computation circuit using static random access memory (SRAM) array segmentation." This circuit comprises a memory array with sub-arrays of SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for in-memory compute operations. The global bit line is capacitively coupled to many local bit lines, allowing for efficient data processing.

Career Highlights

Manuj Ayodhyawasi has worked with leading companies in the technology sector, including STMicroelectronics International N.V. and STMicroelectronics S.R.L. His experience in these organizations has contributed to his expertise in memory circuits and computation technologies.

Collaborations

Throughout his career, Ayodhyawasi has collaborated with talented professionals, including Nitin Chawla and Harsh Rawat. These collaborations have fostered innovation and creativity in his projects.

Conclusion

Manuj Ayodhyawasi is a remarkable inventor whose work in memory circuits and in-memory computation has made a significant impact in the field of technology. His numerous patents reflect his dedication to innovation and excellence.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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