The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2025
Filed:
Jul. 05, 2023
Stmicroelectronics France, Montrouge, FR;
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Stmicroelectronics International N.v., Geneva, CH;
Olivier Weber, Grenoble, FR;
Kedar Janardan Dhori, Ghaziabad, IN;
Promod Kumar, Greater Noida, IN;
Shafquat Jahan Ahmed, Greater Noida, IN;
Christophe Lecocq, Varces, FR;
Pascal Urard, Theys, FR;
STMICROELECTRONICS FRANCE, Montrouge, FR;
STMICROELECTRONICS (CROLLES 2) SAS, Crolles, FR;
STMICROELECTRONICS INTERNATIONAL N.V., Geneva, CH;
Abstract
In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.