logo

For the Inventor, By the Inventor

Fishkill, NY, United States of America

Jun Yuan

This inventor holds 41 USPTO granted patents and 10 published patent applications and 5 EPO patents, primarily in Semiconductor Technology. Top assignees: International Business Machines Corporation, Qualcomm Incorporated, Globalfoundries Inc.. Active years: 2011-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jun Yuan. Retrieved from https://idiyas.com/inventor/jun-yuan-3hyluqaa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 41 

% Patents Active = 53.7

 

Average Co-Inventor Count = 4.3

ph-index = 8

Forward Citations = 208(Granted Patents)


Location History:

  • Hopewell Junction, NY (US) (2011 - 2014)
  • Fishkill, NY (US) (2011 - 2017)
  • San Diego, CA (US) (2014 - 2022)

Company Filing History:

goldMedal23 out of 166,325 
 
International Business Machines Corporation
 patents
silverMedal15 out of 44,831 
 
Qualcomm Incorporated
 patents
bronzeMedal1 out of 5,671 
 
Globalfoundries Inc.
 patents
4. 1 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
5. 1 out of 834,453 
Other
 patents

Years Active: 2011-2026

Loading Chart...
Loading Chart...
Areas of Expertise:
FinFET
CMOS Devices
Non-Volatile Memory
Temperature Sensors
Gate Electrode
Carbon Electronics
Asymmetric FET
High-K Metal Gate
Parasitic Capacitance
Silicon Germanium
Integrated Circuits
Transistor Fabrication
41 patents (USPTO):Explore Patents
1. 12666650 - Field-effect transistors (FETs) employing thermal expansion of work function metal layers for strain effect and related fabrication methods (2026-06-23),
2. 11387335 - Optimized contact structure (2022-07-12),
3. 11257917 - Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication (2022-02-22),
4. 11145654 - Field effect transistor (FET) comprising channels with silicon germanium (SiGe) (2021-10-12),
5. 10854604 - Offset gate contact (2020-12-01),
6. 10247617 - Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) (2019-04-02),
7. 10181403 - Layout effect mitigation in FinFET (2019-01-15),
8. 10141305 - Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts (2018-11-27),
9. 10134734 - Fin field effect transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits employing single and double diffusion breaks for increased performance (2018-11-20),
10. 9997360 - Method for mitigating layout effect in FINFET (2018-06-12),
11. 9876123 - Non-volatile one-time programmable memory device (2018-01-23),
12. 9647169 - Light emitting diode (LED) using carbon materials (2017-05-09),
13. 9601617 - Fabrication of a transistor including a tunneling layer (2017-03-21),
14. 9570442 - Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure (2017-02-14),
15. 9349656 - Method of forming a complementary metal-oxide-semiconductor (CMOS) device (2016-05-24),

Title: Jun Yuan: A Trailblazer in Semiconductor Innovations

Introduction

Jun Yuan is an accomplished inventor based in Fishkill, NY, known for his remarkable contributions to semiconductor technologies. With an impressive portfolio of 40 patents, Yuan has played a pivotal role in advancing the field of electronics. His innovative work is not only shaping the future of technology but also contributing to a more efficient and effective use of semiconductors in various applications.

Latest Patents

Yuan has recently developed several groundbreaking patents. One notable patent is the "Optimized Contact Structure," which involves advanced fabrication techniques for semiconductor dies. This invention focuses on optimizing the contact's structure, where the first portion features a larger cross-sectional area compared to the second portion, ultimately enhancing the die's performance.

Another significant patent is related to "Gate-all-Around (GAA) Transistors with Additional Bottom Channel for Reduced Parasitic Capacitance." This innovation includes intricately designed channels positioned between a source region and a drain region, which are critical for minimizing parasitic capacitance. Such design advancements are crucial for the efficiency and effectiveness of modern semiconductor devices.

Career Highlights

Yuan's career highlights include working with prominent companies such as IBM and Qualcomm. His experience with these leading technology firms has undoubtedly contributed to his exceptional skillset and understanding of the semiconductor industry. His work at these organizations has allowed him to hone his capabilities in innovation and patent development.

Collaborations

Throughout his career, Yuan has collaborated with talented individuals like Dechao Guo and Keith Kwong Hon Wong. These collaborations have focused on pushing the boundaries of semiconductor technology and fostering a culture of innovation within their teams.

Conclusion

Jun Yuan stands out as a significant figure in the realm of semiconductor innovations. With a strong patent portfolio and extensive experience in the industry, he continues to influence and shape the future of technology. His dedication to advancing semiconductor efficiency and functionality showcases his commitment to innovation and excellence.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…