The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Jun. 30, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jun Yuan, San Diego, CA (US);

Yanxiang Liu, San Diego, CA (US);

Kern Rim, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02164 (2013.01); H01L 21/28035 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 29/0649 (2013.01); H01L 29/42376 (2013.01); H01L 29/4916 (2013.01);
Abstract

Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.


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