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For the Inventor, By the Inventor

San Jose, CA, United States of America

Juan J Noguera Serra

This inventor holds 50 USPTO granted patents and 25 published patent applications and 2 EPO patents, primarily in Data Processing Engines. Top assignees: Xilinx, Inc., Advanced Micro Devices Corporation, Trinity College Dublin. Active years: 2011-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Juan J Noguera Serra. Retrieved from https://idiyas.com/inventor/juan-j-noguera-serra

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 50 

% Patents Active = 90.0

 

Average Co-Inventor Count = 5.0

ph-index = 9

Forward Citations = 346(Granted Patents)


Location History:

  • Dublin, IE (2011 - 2015)
  • San Jose, CA (US) (2020 - 2024)

Company Filing History:

goldMedal50 out of 5,116 
 
Xilinx, Inc.
 patents
silverMedal1 out of 13,185 
 
Advanced Micro Devices Corporation
 patents
bronzeMedal1 out of 141 
 
Trinity College Dublin
 patents
where one patent can have more than one assignee

Years Active: 2011-2026

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Areas of Expertise:
Weight Sparsity
Power Reduction
Tiled Compute
Integrated Circuit
Programmable Logic
Multi-Die Circuit
Memory Tiles
Data Selection Network
Stream Interconnect
Partial Reconfiguration
Event-Based Debug
Cascade Streaming
50 patents (USPTO):Explore Patents
1. 12724618 - Controlling a data processing array using an array controller (2026-09-01),
2. 12675420 - Event-based debug, trace, and profile in device with data processing engine array (2026-07-07),
3. 12664120 - Device with data processing engine array that enables partial reconfiguration (2026-06-23),
4. 12656970 - Data processing engine arrangement in a device (2026-06-16),
5. 12639256 - Controllers in data processing engine columns (2026-05-26),
6. 12555036 - Weight sparsity in data processing engines (2026-02-17),
7. 12554310 - Power reduction in an array of data processing engines (2026-02-17),
8. 12536132 - Data processing engine tile architecture for an integrated circuit (2026-01-27),
9. 12505068 - Tiled compute and programmable logic array (2025-12-23),
10. 12401364 - Multiple partitions in a data processing array (2025-08-26),
11. 12261603 - Adaptive integrated programmable device platform (2025-03-25),
12. 12164451 - Data processing array interface having interface tiles with multiple direct memory access circuits (2024-12-10),
13. 12105667 - Device with data processing engine array that enables partial reconfiguration (2024-10-01),
14. 12067406 - Multiple overlays for use with a data processing array (2024-08-20),
15. 12001367 - Multi-die integrated circuit with data processing engine array (2024-06-04),

Title: Inventor Juan J Noguera Serra

Introduction: Juan J Noguera Serra is a renowned inventor based in San Jose, CA (US) known for his groundbreaking innovations in various fields.

Latest Patents: Juan J Noguera Serra holds several patents in the areas of technology, healthcare, and sustainable energy, showcasing his diverse range of expertise.

Career Highlights: With a career spanning over two decades, Juan J Noguera Serra has consistently pushed the boundaries of innovation, leading to significant advancements in the industry.

Collaborations: Throughout his career, Juan J Noguera Serra has collaborated with leading research institutions, universities, and companies to bring his inventions to life, fostering a culture of innovation and progress.

Conclusion: Juan J Noguera Serra's passion for innovation and his dedication to creating impactful solutions have solidified his reputation as a pioneering inventor in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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