The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jul. 18, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Francisco Barat Quesada, Dublin, IE;

Baris Ozgul, Dublin, IE;

Dylan Stuart, Maynooth, IE;

Stephan Münz, Dublin, IE;

Zachary Dickman, Dublin, IE;

Javier Cabezas Rodriguez, Austin, TX (US);

David Patrick Clarke, Dublin, IE;

Pedro Miguel Parola Duarte, Skerries, IE;

Peter Mccolgan, Dublin, IE;

Juan J. Noguera Serra, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06N 20/00 (2019.01);
Abstract

Examples herein describe techniques for reducing the amount of memory used during weight sparsity. When decompressing the weights, the uncompressed weight data typically has many zero values. By knowing the location of these zero values (e.g., their indices in a weight matrix), the processor core can prune some of the activations (e.g., logically reduce the size of the activation matrix) which improves the efficiency of the processor core. In embodiments herein, the processor core includes logic for identifying the indices of the non-zero value after decompressing the compressed weights. These indices can then be used to prune the activations to improve the efficiency of the processor core.


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