The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Aug. 15, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

David Clarke, Dublin, IE;

Juan J. Noguera Serra, San Jose, CA (US);

Javier Cabezas Rodriguez, Austin, TX (US);

Zachary Blaise Dickman, Dublin, IE;

Pedro Miguel Parola Duarte, Dublin, IE;

Jose Marques, Dublin, IE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 9/50 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G06F 17/16 (2006.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 9/5083 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 17/16 (2013.01); G06N 3/063 (2013.01);
Abstract

An integrated circuit includes a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The integrated circuit includes an array controller coupled to the data processing array. The array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application. The application specifies kernels executable by the processors and stream channels that convey data to the plurality of compute tiles. The array controller is configured to initiate execution of workloads by the data processing array as configured with the application.


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