The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Nov. 14, 2023
Xilinx, Inc., San Jose, CA (US);
Juan J. Noguera Serra, San Jose, CA (US);
Tim Tuan, San Jose, CA (US);
Javier Cabezas Rodriguez, Austin, TX (US);
David Clarke, Dublin, IE;
Peter Mccolgan, North Dublin, IE;
Zachary Blaise Dickman, Dublin, IE;
Saurabh Mathur, Saratoga, CA (US);
Amarnath Kasibhatla, Sunnyvale, CA (US);
Francisco Barat Quesada, Dublin, IE;
Xilinx, Inc., San Jose, CA (US);
Abstract
An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.