The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Apr. 15, 2024
Xilinx, Inc., San Jose, CA (US);
Juan J. Noguera Serra, San Jose, CA (US);
Baris Ozgul, Dublin, IE;
Jan Langer, Saxony, DE;
Tim Tuan, San Jose, CA (US);
Ralph D. Wittig, Menlo Park, CA (US);
David Clarke, Walkinstown, IE;
Goran H. K. Bilski, Mölndal, SE;
Kornelis A. Vissers, Sunnyvale, CA (US);
Richard L. Walke, Edinburgh, GB;
Christopher H. Dick, San Jose, CA (US);
Zachary Dickman, Dublin, IE;
Philip B. James-Roxby, Longmont, CO (US);
Peter Mccolgan, Dublin, IE;
Xilinx, Inc., San Jose, CA (US);
Abstract
A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.