Gilbert, AZ, United States of America

Joseph B Petrini

USPTO Granted Patents = 12 

Average Co-Inventor Count = 6.5

ph-index = 2

Forward Citations = 15(Granted Patents)


Company Filing History:


Years Active: 2016-2025

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12 patents (USPTO):Explore Patents

Title: Innovator Profile - Joseph B Petrini: Revolutionizing Thermal Interface Technology

Introduction:

Joseph B Petrini, a prolific inventor based in Gilbert, AZ (US), has made significant contributions to the field of thermal interface technology. With a total of 11 patents to his name, Petrini's innovative work has garnered recognition in the industry.

Latest Patents:

Petrini's recent patents showcase his expertise in thermal interface structures for integrated circuit packages. One notable invention involves a thermal interface structure comprising a thermally conductive substrate with liquid metal layers, designed to enhance heat dissipation in integrated circuit assemblies. Another patent focuses on the application of liquid metal thermal interface material using a specialized presoaked applicator, offering improved thermal conduction for silicon-based devices.

Career Highlights:

Currently affiliated with Intel Corporation, Petrini's role has been pivotal in driving forward advancements in thermal management solutions. His wealth of experience and technical acumen have enabled him to spearhead innovative projects that push the boundaries of thermal interface technology.

Collaborations:

Petrini has collaborated with esteemed colleagues such as Shankar Devasenathipathy and Hemanth K Dhavaleswarapu on various projects. Together, they have shared insights, expertise, and a passion for developing cutting-edge solutions in the realm of thermal management.

Conclusion:

In conclusion, Joseph B Petrini stands as a trailblazer in the field of thermal interface technology, with a remarkable track record of patents that testify to his ingenuity and commitment to innovation. His contributions continue to shape the landscape of thermal management solutions, paving the way for enhanced performance and efficiency in integrated circuit packages.

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