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For the Inventor, By the Inventor

Pleasanton, CA, United States of America

Jongwook Kye

USPTO Granted Patents = 88 

 

Average Co-Inventor Count = 3.2

ph-index = 13

Forward Citations = 681(Granted Patents)

Forward Citations (Not Self Cited) = 672(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Seou, KR (2014)
  • Pleasanton, CA (US) (2002 - 2019)
  • Sunnyvale, CA (US) (2017 - 2020)

Company Filing History:

goldMedal66 out of 5,671 
 
Globalfoundries Inc.
 patents
silverMedal21 out of 12,883 
 
Advanced Micro Devices Corporation
 patents
bronzeMedal1 out of 832,843 
Other
 patents

Years Active: 2002-2020

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Areas of Expertise:
Integrated Circuit Design
Self-Aligned Double Patterning
Transistor Contacts
Circuit Layout Generation
Metal Routing Techniques
FinFET Fabrication
Standard Cell Design
Middle-of-Line Architecture
Diffusion Contact Structures
Patterning Techniques
Semiconductor Device Fabrication
Routing Structures
88 patents (USPTO):Explore Patents
1. 10559503 - Methods, apparatus and system for a passthrough-based architecture (2020-02-11),
2. 10366917 - Methods of patterning variable width metallization lines (2019-07-30),
3. 10347546 - Integrated circuit structure including power rail and tapping wire with method of forming same (2019-07-09),
4. 10204861 - Structure with local contact for shorting a gate electrode to a source/drain region (2019-02-12),
5. 10147714 - Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell (2018-12-04),
6. 10056373 - Transistor contacts self-aligned in two dimensions (2018-08-21),
7. 9818651 - Methods, apparatus and system for a passthrough-based architecture (2017-11-14),
8. 9798852 - Methods of design rule checking of circuit designs (2017-10-24),
9. 9727685 - Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability (2017-08-08),
10. 9679809 - Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines (2017-06-13),
11. 9660040 - Transistor contacts self-aligned two dimensions (2017-05-23),
12. 9613177 - Methods of generating circuit layouts that are to be manufactured using SADP routing techniques (2017-04-04),
13. 9582629 - Methods of generating circuit layouts using self-alligned double patterning (SADP) techniques (2017-02-28),
14. 9536778 - Self-aligned double patterning process for metal routing (2017-01-03),
15. 9536035 - Wide pin for improved circuit routing (2017-01-03),

Title: The Innovative Journey of Jongwook Kye

Introduction: Jongwook Kye, a talented inventor based in Pleasanton, CA, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents: Jongwook Kye's latest patents focus on advancements in artificial intelligence and renewable energy technologies, showcasing his commitment to creating a more sustainable future.

Career Highlights: With a background in engineering and a passion for problem-solving, Jongwook Kye has led successful projects that have revolutionized various industries, earning him recognition as a visionary inventor.

Collaborations: Throughout his career, Jongwook Kye has collaborated with leading research institutions and tech companies to bring his ideas to life, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: Jongwook Kye's dedication to innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors, leaving a lasting impact on the world of technology.

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