Globalfoundries Inc.

Advanced Micro Devices Corporation

Other

Jongwook Kye

Lei Yuan

Harry Jay Levinson

Mahbub Rashed

Jia Zeng

Yunfei Deng

Youngtag Woo

Jason Eugene Stephens

Yan E Wang

Yuansheng Ma

Guillaume Bouche

Suresh Venkatesan

Juhan Kim

Tuhin Guha Neogi

Dinesh Somasekhar

Subramani Kengeri

Wenhui Wang

Bruno M La Fontaine

Irene Y Lin

Soo Han Choi

Hidekazu Yoshida

Chenchen Wang

Christopher F Lyons

Li Ping Yang

Carl P Babcock

Andy Chih-Hung Wei

Bruno M LaFontaine

Thomas Ingolf Wallow

Jin Haeng Cho

Mark Alexander Zaleski

Ryoung-han Kim

Xuelian Zhu

David Doman

Rod Augur

Irene Yuh-Ling Lin

Qi Xiang

Cyrus E Tabery

Scott C Johnson

Marc Laurent Tarabbia

Navneet Jain

Hyeon-Seag Kim

Ivan Lalovic

Sudharshanan Raghunathan

Adam R Pawloski

Chinh Nguyen

Jeff Kim

Alden R Acheta

Andy Chi-Hung Wei

Seung-Hyun Rhee

Ramkumar Subramanian

Ali Keshavarzi

Shibly S Ahmed

Ryan Ryoung-Han Kim

Steven R Soss

Hung-Eil Kim

Anna Maria Minvielle

Ingolf Lorenz

Yuan Lei

Qinglei Wang

James B Gullette

Larry Ho

James Benjamin Gullette

Myungjun Lee

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

Methods, apparatus and system for a passthrough-based architecture

Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.

Methods of patterning variable width metallization lines

The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

Integrated circuit structure including power rail and tapping wire with method of forming same

The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

Structure with local contact for shorting a gate electrode to a source/drain region

At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell

Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Transistor contacts self-aligned in two dimensions

Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Methods of design rule checking of circuit designs

At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability

A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines

Transistor contacts self-aligned two dimensions

One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

Methods of generating circuit layouts that are to be manufactured using SADP routing techniques

At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Methods of generating circuit layouts using self-alligned double patterning (SADP) techniques

Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Self-aligned double patterning process for metal routing

Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Wide pin for improved circuit routing

Growing community of inventors

Pleasanton, CA, United States of America

Jongwook Kye