The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jul. 27, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Lei Yuan, Cupertino, CA (US);

Juhan Kim, Santa Clara, CA (US);

Jongwook Kye, Pleasanton, CA (US);

Mahbub Rashed, Cupertino, CA (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); G06F 17/50 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.


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