The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2017
Filed:
Mar. 22, 2016
Globalfoundries Inc., Grand Cayman, KY;
Jongwook Kye, Pleasanton, CA (US);
Yan Wang, San Jose, CA (US);
Chenchen Wang, Sunnyvale, CA (US);
Wenhui Wang, Santa Clara, CA (US);
Lei Yuan, Cupertino, CA (US);
Jia Zeng, Sunnyvale, CA (US);
Guillaume Bouche, Albany, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.