Fort Collins, CO, United States of America

Jeffrey R Rearick

This inventor holds 23 USPTO granted patents, primarily in Integrated Circuit Testing. Top assignees: Agilent Technologies, Inc., Avago Technologies General IP (Singapore) Pte. Ltd., Avago Technologies General IP Pte, Ltd.. Active years: 2000-2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeffrey R Rearick. Retrieved from https://idiyas.com/inventor/jeffrey-r-rearick

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 65.2

Average Co-Inventor Count = 2.7

ph-index = 10

Forward Citations = 253(Granted Patents)


Location History:

  • Ft. Collins, CO (US) (2000)
  • Fort Collins, CO (US) (2003 - 2009)

Company Filing History:


Years Active: 2000-2009

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Areas of Expertise:
Embedded Time Domain Reflectometry
Clock Period Elongation
Memory Device Remapping
Scan Chain Reconfiguration
Delay-Locked Loop
Test Coverage Analysis
Pad Driver Testing
Automated Test Equipment
Circuit Performance Comparison
Test Pattern Generator
Receiver Termination Testing
Programmable Hysteresis
23 patents (USPTO):Explore Patents

Title: **Jeffrey R Rearick: Innovator in Integrated Circuit Testing**

Introduction

Jeffrey R Rearick is a notable inventor based in Fort Collins, Colorado, with an impressive portfolio of 23 patents. His contributions to the field of integrated circuit testing have greatly influenced technology development, particularly in enhancing the reliability and performance of integrated circuits.

Latest Patents

Among his latest inventions, Rearick has developed a "Method and Apparatus for an Embedded Time Domain Reflectometry Test." This inventive approach allows for the testing of integrated circuit interconnects by utilizing embedded circuitry within the IC to perform pseudo time domain reflectometry tests. By launching a test transition onto the interconnect and capturing reflections, this method improves testing accuracy and efficiency.

Another significant patent is the "Apparatus and Method for Compensating Clock Period Elongation During Scan Testing in an Integrated Circuit." This invention addresses the challenges of clock period elongation by operating a clock associated with the IC at a desired frequency. The process involves measuring actual clock periods, determining delays, and adjusting the clock frequency during scan testing to ensure optimal IC performance.

Career Highlights

Jeffrey Rearick has had a distinguished career working with leading technology companies. He has contributed his expertise at Agilent Technologies, Inc. and Avago Technologies General IP (Singapore) Pte. Ltd., where he has played a key role in the advancement of integrated circuit technologies. His work has not only added to his patent portfolio but has also influenced the broader technology landscape.

Collaborations

Throughout his career, Rearick has collaborated with notable colleagues, including John G Rohrbaugh and Shad R Shepston. These partnerships have fostered innovation and development in the fields of electronics and integrated circuit testing, showcasing the power of teamwork in driving technological progress.

Conclusion

Jeffrey R Rearick's contributions to the field of integrated circuits through his innovative patents and collaborations with esteemed companies highlight his significant impact on technology. As he continues to push the boundaries of what is possible in IC testing, his work remains an inspiration for future inventors and engineers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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