The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Jun. 16, 2004
Alvin Leng Sun Loke, Fort Collins, CO (US);
Michael Joseph Gilsdorf, Fort Collins, CO (US);
Peter Jacob Meier, Fort Collins, CO (US);
Jeffrey R. Rearick, Fort Collins, CO (US);
Alvin Leng Sun Loke, Fort Collins, CO (US);
Michael Joseph Gilsdorf, Fort Collins, CO (US);
Peter Jacob Meier, Fort Collins, CO (US);
Jeffrey R. Rearick, Fort Collins, CO (US);
Agilent Technologies, Inc., Palo Alto, CA (US);
Abstract
A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the dock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.