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For the Inventor, By the Inventor

Fort Collins, CO, United States of America

Peter Jacob Meier

This inventor holds 18 USPTO granted patents and 3 published patent applications, primarily in Integrated Circuit Design. Top assignees: Agilent Technologies, Inc., Avago Technologies General IP (Singapore) Pte. Ltd., Hewlett-Packard Company. Active years: 1992-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter Jacob Meier. Retrieved from https://idiyas.com/inventor/peter-jacob-meier

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18 

% Patents Active = 77.8

Average Co-Inventor Count = 3.0

ph-index = 8

Forward Citations = 312(Granted Patents)


Location History:

  • Ft. Collins, CO (US) (1995 - 2004)
  • Fort Collins, CO (US) (1992 - 2017)

Company Filing History:

goldMedal5 out of 4,741 
 
Agilent Technologies, Inc.
 patents
silverMedal5 out of 1,813 
 
Avago Technologies General IP (Singapore) Pte. Ltd.
 patents
bronzeMedal5 out of 9,639 
 
Hewlett-Packard Company
 patents
4. 2 out of 28 
 
Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
 patents
5. 1 out of 55 
 
Avago Technologies General IP Pte, Ltd.
 patents

Years Active: 1992-2017

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Areas of Expertise:
Data Parallelization
Delay-Locked Loop
Integrated Circuit
Clock Synchronization
SERDES
Mask Data Generation
High Voltage Tolerant
Source Synchronous Clocking
Transition Density
Clock Domains
Register Calibration
Buffer Inverter
18 patents (USPTO):Explore Patents
1. 9767062 - Low power parallelization to multiple output bus widths (2017-09-19),
2. 8902091 - System and method for high speed data parallelization for an N-phase receiver (2014-12-02),
3. 8634503 - Fast lock clock-data recovery for phase steps (2014-01-21),
4. 7742427 - Internal loop-back architecture for parallel serializer/deserializer (SERDES) (2010-06-22),
5. 7548174 - System and method for equalizing transition density in an integrated circuit (2009-06-16),
6. 7526744 - Integrated circuit design method for efficiently generating mask data (2009-04-28),
7. 7352165 - Delay-locked loop and a method of testing a delay-locked loop (2008-04-01),
8. 7123001 - Delay-locked loop and a method of testing a delay-locked loop (2006-10-17),
9. 6995554 - Delay-locked loop and a method of testing a delay-locked loop (2006-02-07),
10. 6744285 - Method and apparatus for synchronously transferring data across multiple clock domains (2004-06-01),
11. 6665218 - Self calibrating register for source synchronous clocking systems (2003-12-16),
12. 6539507 - Integrated circuit with alternately selectable state evaluation provisions (2003-03-25),
13. 6124869 - Method and apparatus for low cost set mapping (2000-09-26),
14. 5847969 - Integrated circuit design system and method for generating a regular (1998-12-08),
15. 5646809 - High voltage tolerant CMOS input/output pad circuits (1997-07-08),

Title: **Innovative Contributions of Peter Jacob Meier in Fort Collins, CO**

Introduction

Peter Jacob Meier is a noteworthy inventor based in Fort Collins, Colorado, known for his significant contributions to the field of data transmission technology. With a remarkable portfolio of 18 patents, he has demonstrated a commitment to enhancing the efficiency and functionality of communication systems.

Latest Patents

Meier's latest innovations include a groundbreaking Serializer/Deserializer (SerDes) that emphasizes low power parallelization to accommodate multiple output bus widths. This innovative architecture not only allows for flexibility across various gear ratios but also prioritizes reduced power consumption by utilizing latches instead of traditional flip-flops. Furthermore, the SerDes incorporates a main register bank with multiple sub-banks, which can be filled using a variety of schemes to support differing output widths.

Another of his notable patents focuses on a system and method for high-speed data parallelization within an N-phase receiver. This design features a serial-to-parallel converter comprising multiple register banks, configured to enhance the processing of communication signals while maintaining high efficiency across various stages.

Career Highlights

Throughout his illustrious career, Peter Jacob Meier has been associated with leading companies in the technology sector, including Hewlett-Packard Company and Agilent Technologies, Inc. His work in these organizations has been instrumental in advancing communication technology, further solidifying his reputation as a forward-thinking inventor.

Collaborations

Meier has also collaborated with esteemed colleagues such as Brian C. Miller and Gordon W. Motley, contributing to collective efforts that drive innovation within their field. These collaborations showcase the importance of teamwork in the technological advancements that Meier has been a part of.

Conclusion

In summary, Peter Jacob Meier stands out as a prolific inventor whose work has significantly impacted the domain of data transmission technology. His inventive spirit, exemplified through his 18 patents and collaborations with industry peers, continues to influence the evolution of communication systems, ensuring efficiency and performance for future technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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