The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Apr. 17, 2015
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Darrin C. Miller, Fort Collins, CO (US);

Peter J. Meier, Fort Collins, CO (US);

Gilbert Yoh, Fort Collins, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 1/08 (2006.01); G06F 3/06 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 1/08 (2013.01); G06F 3/0656 (2013.01); G06F 13/385 (2013.01); G06F 13/387 (2013.01); G06F 13/4059 (2013.01); G06F 13/4282 (2013.01); G11C 2207/107 (2013.01); H03M 2201/526 (2013.01);
Abstract

A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.


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