Hewlett-packard Company

Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Peter Jacob Meier

Brian C Miller

Jeffrey R Rearick

Alvin Leng Sun Loke

Robert James Martin

Gordon W Motley

Michael Joseph Gilsdorf

David Steven Maitland

Gilbert Yoh

Michael Farmer

Darrin C Miller

Jade M Kizer

Brian James Misek

Robert Keith Barnes

Michael R Diehl

Dale Beucler

Joel D Buck-Gengler

Gerald L Esch, Jr

Kenneth S Bower

Rory L Fisher

Christopher M Juenemann

Cory Groth

Randy L Fiscus

Bradley J Goertzen

Anthony J Abeyta, Jr

Ken DelGrande

Wayne G Mangum

A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Low power parallelization to multiple output bus widths

A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.

System and method for high speed data parallelization for an N-phase receiver

A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Fast lock clock-data recovery for phase steps

An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.

Internal loop-back architecture for parallel serializer/deserializer (SERDES)

A system for equalizing transition density in an integrated circuit includes a first circuit configured to transition according to a data stream; and a second circuit configured to transition at a time when the first circuit is not transitioning.

System and method for equalizing transition density in an integrated circuit

A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the set of routing definitions to locate and size conductors modeled in the mask data. A design tool includes a memory and a processor. The memory stores routing definitions that enable conductor routing schemes having the same cell pitch. The processor receives an input identifying a select routing definition from the set of routing definitions. The processor executes logic that generates an array of points responsive to a characteristic of the routing definitions. The processor further executes logic configured to constrain the relative location and width of conductors in the integrated circuit.

Integrated circuit design method for efficiently generating mask data

A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

Delay-locked loop and a method of testing a delay-locked loop

A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the dock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.

Method and apparatus for synchronously transferring data across multiple clock domains

A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.

Self calibrating register for source synchronous clocking systems

An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

Integrated circuit with alternately selectable state evaluation provisions

A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.

Method and apparatus for low cost set mapping

An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.

Integrated circuit design system and method for generating a regular

A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage.

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Fort Collins, CO, United States of America

Peter Jacob Meier