The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Apr. 06, 2004
Richard S. Rodgers, Fort Collins, CO (US);
Jeffrey R. Rearick, Fort Collins, CO (US);
Cory D. Groth, Fort Collins, CO (US);
Richard S. Rodgers, Fort Collins, CO (US);
Jeffrey R. Rearick, Fort Collins, CO (US);
Cory D. Groth, Fort Collins, CO (US);
Avago Technologies General IP Pte. Ltd., Singapore, SG;
Abstract
An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK_OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN_CLOCK_OUT) at the clock output, determining a delay by calculating the difference between TSCAN_CLOCK_OUT and TOLOCK_OUT, and compensating for the delay by increasing the clock frequency during scan test.