The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2009

Filed:

Mar. 27, 2006
Applicants:

Richard S. Rodgers, Fort Collins, CO (US);

Jeffrey R. Rearick, Fort Collins, CO (US);

Cory D. Groth, Fort Collins, CO (US);

Inventors:

Richard S. Rodgers, Fort Collins, CO (US);

Jeffrey R. Rearick, Fort Collins, CO (US);

Cory D. Groth, Fort Collins, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/14 (2006.01); G01R 35/00 (2006.01); G01D 18/00 (2006.01); G01D 21/00 (2006.01); G01P 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (f) at which IC operation is sought to be determined, measuring the actual clock period (T) at a clock output, scan testing the IC, measuring the actual clock period (T) at the clock output, determining a delay by calculating the difference between Tand T, and compensating for the delay by increasing the clock frequency during scan test.


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