Santa Clara, CA, United States of America

Jayabrata Ghosh Dastidar

This inventor holds 24 USPTO granted patents, primarily in Integrated Circuit Testing. Top assignee: Altera Corporation. Active years: 2006-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jayabrata Ghosh Dastidar. Retrieved from https://idiyas.com/inventor/jayabrata-ghosh-dastidar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24

% Patents Active = 33.3

Average Co-Inventor Count = 1.8

ph-index = 8

Forward Citations = 185(Granted Patents)

Location History:

San Jose, CA (US) (2007 - 2010)
Santa Clara, CA (US) (2006 - 2013)
Campbell, CA (US) (2013 - 2015)

Company Filing History:

24 out of 4,333

Altera Corporation

patents

Years Active: 2006-2015

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Areas of Expertise:

Clock Control Circuitry

Die Testing

Test Pattern Generation

Configurable Test Pins

Built-In Self-Test

Logic Circuit Testing

Power Supply Voltage Testing

Pipelined Scan Structures

Yield Monitoring

Programmable Logic Devices

Failure Isolation

Security Data Encryption

24 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9075112 - Clock control circuitry and methods of utilizing the clock control circuitry (2015-07-07),

2. 8952713 - Method and apparatus for die testing (2015-02-10),

3. 8621303 - Clock control circuitry and methods of utilizing the clock control circuitry (2013-12-31),

4. 8516322 - Automatic test pattern generation system for programmable logic devices (2013-08-20),

5. 8327199 - Integrated circuit with configurable test pins (2012-12-04),

6. 8259522 - Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks (2012-09-04),

7. 8004915 - Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks (2011-08-23),

8. 7996743 - Logic circuit testing with reduced overhead (2011-08-09),

9. 7707472 - Method and apparatus for routing efficient built-in self test for on-chip circuit blocks (2010-04-27),

10. 7571413 - Testing circuitry for programmable logic devices with selectable power supply voltages (2009-08-04),

11. 7502979 - Pipelined scan structures for testing embedded cores (2009-03-10),

12. 7475315 - Configurable built in self test circuitry for testing memory arrays (2009-01-06),

13. 7424658 - Method and apparatus for testing integrated circuits (2008-09-09),

14. 7409669 - Automatic test configuration generation facilitating repair of programmable circuits (2008-08-05),

15. 7373621 - Constraint-driven test generation for programmable logic device integrated circuits (2008-05-13),

Title: Spotlight on Innovator Jayabrata Ghosh Dastidar

Introduction:

Jayabrata Ghosh Dastidar, a prolific inventor based in Santa Clara, CA, has made significant contributions to the world of technology with an impressive portfolio of 24 patents. His innovative spirit and expertise in the field have led to groundbreaking developments in circuitry design and device testing.

Latest Patents:

1. Clock Control Circuitry: Jayabrata's cutting-edge design-for-test (DFT) circuitry includes a first multiplexer for transferring clock signals, a burst counter for predefined pulse counts, and various multiplexers for signal control. This invention enhances clock signal utilization in circuitry design.

2. Method and Apparatus for Die Testing: His device tester innovation features a probe card, substrate with signal routing layers, and an integrated circuit for transmitting and amplifying test signals between testing apparatus and devices under test. This invention revolutionizes die testing processes.

Career Highlights:

Jayabrata Ghosh Dastidar shines as an asset at Altera Corporation, where he is instrumental in driving innovation and technological advancements. His passion for problem-solving and creating impactful solutions has cemented his reputation as a leading figure in the tech industry.

Collaborations:

Collaborating with talented individuals like Michael Harms and Paul J Tracy has further propelled Jayabrata's inventive endeavors. Together, they have synergized their skills and expertise to push the boundaries of technology and achieve remarkable results in their projects.

Conclusion:

In conclusion, Jayabrata Ghosh Dastidar stands as a visionary inventor, whose dedication to advancing technology has resulted in a remarkable patent portfolio. His work at Altera Corporation and collaborations with esteemed colleagues underscore his commitment to pushing the boundaries of innovation and driving progress in the tech industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]