Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks

Abstract

An integrated circuit is provided with built-in-self test circuitry. The integrated circuit may have multiple blocks of memory. The memory may be tested using the built-in-self test circuitry. Each memory block may include a satellite address generator that is used in generating test addresses for the memory blocks. Each memory block may also include failure analysis logic and output response analyzer logic. Stalling logic may be used to individually stall memory block testing on a block-by-block basis during memory tests. Address buffer circuitry such as first-in-first-out buffers may be used to provide randomized memory addresses during testing.