The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Feb. 01, 2005
Jayabrata Ghosh Dastidar, San Jose, CA (US);
Jayabrata Ghosh Dastidar, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device test generation tool is provided that produces test configuration data and test vectors for testing programmable logic device integrated circuits. A graph generation tool converts a netlist or other circuit description of a programmable logic device integrated circuit into a graph having nodes and edges. A timing analysis tool may be used to help produce test constraints. Based on the test constraints, an automatic test generator processes the graph to produce the test configuration data and test vectors. In processing the graph with the automatic test generator, the graph may be divided into multiple testable subgraphs. Each subgraph may be processed using an iterative approach in which a cost function threshold is adjusted in a number of steps until a target test coverage is obtained or processing saturates.