The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
Apr. 01, 2008
Tze Sin Tan, Penang, MY;
Jayabrata Ghosh Dastidar, Santa Clara, CA (US);
Tze Sin Tan, Penang, MY;
Jayabrata Ghosh Dastidar, Santa Clara, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.