The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2009

Filed:

Jan. 10, 2007
Applicants:

Balaji Natarajan, Santa Clara, CA (US);

Jayabrata Ghosh Dastidar, Santa Clara, CA (US);

Muhammad Naziri Zakaria, Gelugor, MY;

Inventors:

Balaji Natarajan, Santa Clara, CA (US);

Jayabrata Ghosh Dastidar, Santa Clara, CA (US);

Muhammad Naziri Zakaria, Gelugor, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The built in self test circuitry may have test control register circuitry and configurable state machine logic. The state machine logic may perform at-speed tests on a memory array and may provide test results to external equipment for analysis. A tester may be used to provide test control settings to the test control register circuitry. The test control settings may include march element settings for a march sequence. During testing, the configurable state machine logic may use the march element settings to generate march sequences. March sequences that have been generated in this way may be used in testing the memory array.


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