The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7707472 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 27, 2010

Filed:

May. 17, 2004
Applicant:

Jayabrata Ghosh Dastidar, San Jose, CA (US);

Inventor:

Jayabrata Ghosh Dastidar, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Built-in self test techniques for testing circuit blocks on integrated circuits are provided. A BIST controller is provided on-chip to test two or more circuit blocks. High routing congestion is avoided by loading test data into the circuit blocks through scan chain segments that run continuously along the inputs and outputs of the circuit blocks. The BIST controller takes control of the scan chain segments during test and has the ability to partition the scan chains at specified intervals.


Find Patent Forward Citations

Dastidar, Jayabrata. (2010). Method and apparatus for routing efficient built-in self test for on-chip circuit blocks (U.S. Patent No. 7707472). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7707472

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