Jasmeet S Chawla

This inventor holds 20 USPTO granted patents and 3 published patent applications and 5 EPO patents. Top assignees: Intel Corporation, Tahoe Research, Ltd.. Active years: 2015-2025.

USPTO Granted Patents = 20 (Patent Applications = 3)

% Patents Active = 75.0

EPO Patents = 5 (Patent Applications = 7)

Average Co-Inventor Count = 4.1

ph-index = 5

Forward Citations = 88(Granted Patents)

Location History:

Beaverton, OR (US) (2021)
Hillsboro, OR (US) (2015 - 2022)

Company Filing History:

Years Active: 2015-2025

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20 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12394716 - Integrated circuit interconnect structures with graphene cap (2025-08-19),

2. 12322699 - Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches (2025-06-03),

3. 11380617 - Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches (2022-07-05),

4. 11107908 - Transistors with metal source and drain contacts including a Heusler alloy (2021-08-31),

5. 11069609 - Techniques for forming vias and other interconnects for integrated circuit structures (2021-07-20),

6. 11056593 - Semiconductor devices with metal contacts including crystalline alloys (2021-07-06),

7. 10971394 - Maskless air gap to prevent via punch through (2021-04-06),

8. 10957844 - Magneto-electric spin orbit (MESO) structures having functional oxide vias (2021-03-23),

9. 10707186 - Compliant layer for wafer to wafer bonding (2020-07-07),

10. 10546772 - Self-aligned via below subtractively patterned interconnect (2020-01-28),

11. 10497613 - Microelectronic conductive routes and methods of making the same (2019-12-03),

12. 10256141 - Maskless air gap to prevent via punch through (2019-04-09),

13. 10109583 - Method for creating alternate hardmask cap interconnect structure with increased overlay margin (2018-10-23),

14. 10032643 - Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme (2018-07-24),

15. 9911694 - Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches (2018-03-06),

Title: The Innovative Journey of Jasmeet S Chawla

Introduction: Jasmeet S Chawla, a talented inventor based in Hillsboro, Oregon, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Jasmeet S Chawla holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his diverse expertise and forward-thinking approach to problem-solving.

Career Highlights: With a background in engineering and a passion for creating solutions that make a difference, Jasmeet S Chawla has had a successful career marked by his ability to turn innovative ideas into tangible products that have a positive impact on society.

Collaborations: Throughout his career, Jasmeet S Chawla has collaborated with leading research institutions, universities, and tech companies to further develop and commercialize his inventions, demonstrating his commitment to pushing the boundaries of technological advancement.

Conclusion: Jasmeet S Chawla's dedication to innovation and his relentless pursuit of excellence have solidified his reputation as a visionary inventor in the tech industry, with his work continuing to inspire future generations of innovators.