The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Sep. 07, 2018
Intel Corporation, Santa Clara, CA (US);
Mauro J. Kobrinsky, Portland, OR (US);
Jasmeet S. Chawla, Hillsboro, OR (US);
Stefan Meister, Portland, OR (US);
Myra McDonnell, Portland, OR (US);
Chytra Pawashe, Beaverton, OR (US);
Daniel Pantuso, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.